module tx_ctrl (
    input                       clk         ,
    input                       rst_n       ,
    input           [2:0]       key_down    ,
    input                       tx_done     ,
    input           [23:0]      out_data    ,
    input                       data_vld    ,
    output                      tx_start    ,
    output   reg    [ 7:0]      tx_data 
);

//字节计数器

reg		[5:0]	cnt_byte	    ;
wire			add_cnt_byte    ;
wire			end_cnt_byte    ;
reg             cnt_byte_flg    ;

reg     [1:0]   state           ;

always @(posedge clk or negedge rst_n)begin 
    if(!rst_n)begin
        state <= 2'b0;
    end 
    else if(key_down[0])begin 
        state <= 2'b1;
    end 
    else if(key_down[1])begin 
        state <= 2'd2;
    end 
    else if(end_cnt_byte)begin
        state <= 2'd0;
    end
end

always @(posedge clk or negedge rst_n)begin 
   if(!rst_n)begin
        cnt_byte <= 'd0;
    end 
    else if(add_cnt_byte)begin 
        if(end_cnt_byte)begin 
            cnt_byte <= 'd0;
        end
        else begin 
            cnt_byte <= cnt_byte + 1'b1;
        end 
    end
end 

assign add_cnt_byte = tx_done && cnt_byte_flg;
assign end_cnt_byte = add_cnt_byte && cnt_byte == 17-1;

always @(posedge clk or negedge rst_n)begin 
    if(!rst_n)begin
        cnt_byte_flg <= 'd0;
    end 
    else if(end_cnt_byte)begin 
        cnt_byte_flg <= 'd0;
    end 
    else if(data_vld)begin 
        cnt_byte_flg <= 'd1;
    end 
end

always @(*)begin
        case(cnt_byte)
            0       :   tx_data   <=  (state == 1) ? 8'hc9 : ((state == 2) ? 8'hb6 : 8'hc9);
            1       :   tx_data   <=  (state == 1) ? 8'he8 : ((state == 2) ? 8'hc1 : 8'he8);
            2       :   tx_data   <=  (state == 1) ? 8'hb1 : ((state == 2) ? 8'hca : 8'hb1);
            3       :   tx_data   <=  (state == 1) ? 8'hb8 : ((state == 2) ? 8'hfd : 8'hb8);
            4       :   tx_data   <=  (state == 1) ? 8'h49 : ((state == 2) ? 8'hbe : 8'h49);
            5       :   tx_data   <=  (state == 1) ? 8'h44 : ((state == 2) ? 8'hdd : 8'h44);
            6       :   tx_data   <=  8'h3a;
            7       :   tx_data   <=  8'h20;
            8       :   tx_data   <=  (out_data [23:20]< 4'd10) ? out_data [23:20]+6'd48 : out_data [23:20]+6'd55;
            9       :   tx_data   <=  (out_data [19:16]< 4'd10) ? out_data [19:16]+6'd48 : out_data [19:16]+6'd55;
            10      :   tx_data   <=  8'h20;
            11      :   tx_data   <=  (out_data [15:12]< 4'd10) ? out_data [15:12]+6'd48 : out_data [15:12]+6'd55;
            12      :   tx_data   <=  (out_data [11:8] < 4'd10) ? out_data [11:8] +6'd48 : out_data [11:8] +6'd55;
            13      :   tx_data   <=  8'h20;
            14      :   tx_data   <=  (out_data [7:4]  < 4'd10) ? out_data [7:4]  +6'd48 : out_data [7:4]  +6'd55;
            15      :   tx_data   <=  (out_data [3:0]  < 4'd10) ? out_data [3:0]  +6'd48 : out_data [3:0]  +6'd55;
            16      :   tx_data   <=  8'h0a;
            default :   tx_data   <=  8'h0;
        endcase
end

assign tx_start =  cnt_byte_flg;
    
endmodule